bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
| 此处几行代码，注释中写的也很清楚了，就是去清楚对应的位和设置对应的位，具体位域的含义见下： http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0184b/Chdifbjc.html 表 1.6. 控制寄存器1的位域含义 | Register bits | Name | Function | Value |
|---|
| 31 | iA bit | Asynchronous clock select | See Table 2.11 | | 30 | nF bit | notFastBus select | See Table 2.11 | | 29:15 | - | Reserved | Read = Unpredictable
Write = Should be zero | | 14 | RR bit | Round robin replacement | 0 = Random replacement
1 = Round-robin replacement | | 13 | V bit | Base location of exception registers | 0 = Low addresses = 0x00000000
1 = High addresses = 0xFFFF0000 | | 12 | I bit | ICache enable | 0 = ICache disabled
1 = ICache enabled | | 11:10 | - | Reserved | | | 9 | R bit | ROM protection | This bit modifies the MMU protection system. See Domain access control | | 8 | S bit | System protection | This bit modifies the MMU protection system. See Domain access control | | 7 | B bit | Endianness | 0 = Little-endian operation
1 = Big-endian operation | | 6:3 | - | Reserved | | | 2 | C bit | DCache enable | 0 = DCache disabled
1 = DCache enabled | | 1 | A bit | Alignment fault enable | Data address alignment fault checking0 = Fault checking disabled
1 = Fault checking enabled | | 0 | M bit | MMU enable | 0 = MMU disabled
1 = MMU enabled |
表 1.7. 时钟模式 | Clocking mode | iA | nF |
|---|
| FastBus mode | 0 | 0 | | Synchronous | 0 | 1 | | Reserved | 1 | 0 | | Asynchronous | 1 | 1 |
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0151c/I273867.html Domain access control 表 1.8. 关于访问控制位在域访问控制寄存器中的含义 | Value | Meaning | Description |
|---|
| 00 | No access | Any access generates a domain fault | | 01 | Client | Accesses are checked against the access permission bits in the section or page descriptor | | 10 | Reserved | Reserved. Currently behaves like the no access mode | | 11 | Manager | Accesses are not checked against the access permission bits so a permission fault cannot be generated |
表 1.9 “关于访问允许(AP)位的含义”shows how to interpret the Access Permission (AP) bits and how their interpretation is dependent on the S and R bits (control register bits 8 and 9) 表 1.9. 关于访问允许(AP)位的含义 | AP | S | R | Supervisor permissions | User permissions | Description |
|---|
| 00 | 0 | 0 | No access | No access | Any access generates a permission fault | | 00 | 1 | 0 | Read-only | No access | Only Supervisor read permitted | | 00 | 0 | 1 | Read-only | Read-only | Any write generates a permission fault | | 00 | 1 | 1 | Reserved | - | - | | 01 | x | x | Read/write | No access | Access allowed only in Supervisor mode | | 10 | x | x | Read/write | Read-only | Writes in User mode cause permission fault | | 11 | x | x | Read/write | Read/write | All access types permitted in both modes | | xx | 1 | 1 | Reserved | - | |
|
| 此行作用是： - 清除bit[13]
Base location of exception register(异常寄存器基地址) 0 = Low address = 0x0000 0000 - 清除bit[9]和bit[8]
此处不是很懂，待后续深入了解。 目前的理解是： 不论是Supervisor还是user，谁都不能访问，否则就出现权限错误“Any access generates a permission fault”
|
| 此行作用是： - 清除bit[7]
使用little endian - 清除bit[2-0]
DCache disabled,关闭Dcache； Alignment Fault checking disabled，关闭地址对齐的错误检查； MMU disabled，关闭MMU。
|
| 此行作用是： - 设置bit[1]
“Enable Data address alignment fault checking”打开数据地址对齐的错误检查，即如果数据地址为非法（奇数？）地址，就报错。
|
| 此行作用是： |
| mcr指令，将刚才设置的r0的值，再写入到寄存器1中。 |
