1.8. PL08X macros

/*
 * Power Management.
 * PM support is not complete. Turn it off.1
 */
#undef CONFIG_PM

#ifdef CONFIG_PM
#else
# define pl08x_do_suspend	NULL
# define pl08x_do_resume 	NULL
# define pl08x_suspend		NULL
# define pl08x_resume		NULL
#endif

#ifdef MODULE

# error "AMBA PL08X DMA CANNOT BE COMPILED AS A LOADABLE MODULE AT PRESENT"

/*
	a) Some devices might make use of DMA during boot
	   (esp true for DMAENGINE implementation)
	b) Memory allocation will need much more attention
	   before load/unload can be supported
 */
#endif

struct pl08x_driver_data pd;

/*
 * PL08X specific defines
 */
/* Minimum period between work queue runs */
#define PL08X_WQ_PERIODMIN	20
/* Size (bytes) of each buffer allocated for one transfer */
# define PL08X_LLI_TSFR_SIZE	0x20002
/* Maximimum times we call dma_pool_alloc on this pool without freeing */
# define PL08X_MAX_ALLOCS	0x40
#define MAX_NUM_TSFR_LLIS 	(PL08X_LLI_TSFR_SIZE/sizeof(struct _lli))3
#define PL08X_ALIGN		8
#define PL08X_ALLOC		0

/* Register offsets */4
#define	PL08X_OS_ISR		0x00
#define	PL08X_OS_ISR_TC		0x04
#define	PL08X_OS_ICLR_TC	0x08
#define	PL08X_OS_ISR_ERR	0x0C
#define	PL08X_OS_ICLR_ERR	0x10
#define	PL08X_OS_CFG		0x30
#define	PL08X_OS_CCFG		0x10
#define	PL08X_OS_ENCHNS		0x1C
#define	PL08X_OS_CHAN		0x20
#define	PL08X_OS_CHAN_BASE	0x100

/* Channel registers */5
#define	PL08X_OS_CSRC		0x00
#define	PL08X_OS_CDST		0x04
#define	PL08X_OS_CLLI		0x08
#define	PL08X_OS_CCTL		0x0C
/* register masks */
#define	PL08X_MASK_CFG		0xFFFFFFF1
#define	PL08X_MASK_EN		0x00000001
#define	PL08X_MASK_CLLI		0x00000002
#define	PL08X_MASK_TSFR_SIZE	0x00000FFF
#define	PL08X_MASK_INTTC	0x00008000
#define	PL08X_MASK_INTERR	0x00004000
#define	PL08X_MASK_CCFG		0x00000000
#define	PL08X_MASK_HALT		0x00040000
#define	PL08X_MASK_ACTIVE	0x00020000
#define	PL08X_MASK_CEN		0x00000001
#define	PL08X_MASK_ENCHNS	0x000000FF
#define PL08X_WIDTH_8BIT	0x00
#define PL08X_WIDTH_16BIT	0x01
#define PL08X_WIDTH_32BIT	0x02

/*6
 * Transferring less than this number of bytes as bytes
 * is faster than calculating the required LLIs....
 * (8 is the real minimum
 * >7 bytes must have a word alignable transfer somewhere)
 */
#define PL08X_BITESIZE		0x10
/*
 * Flow control bit masks7
 */
#define PL08X_FCMASK_M2M_DMA	0x00000000
#define PL08X_FCMASK_M2P_DMA	0x00000800
#define PL08X_FCMASK_P2M_DMA	0x00001000
#define PL08X_FCMASK_P2P_DMA	0x00001800
#define PL08X_FCMASK_P2P_DST	0x00002000
#define PL08X_FCMASK_M2P_PER	0x00002800
#define PL08X_FCMASK_P2P_PER	0x00003000
#define PL08X_FCMASK_P2P_SRC	0x00003800
/* Max number of transfers which can be coded in the control register */
#define PL08X_MAX_TSFRS		0xFFF

#define PL08X_CODING_ERR	0xFFFFFFFF
        

1

暂时没有实现Linux中PM 的支持

2

对于其他使用此DMA 的驱动中,会去提交DMA请求,此处就是指一次DMA请求中,最大所允许的传输大小,此处是0x2000= 8192

3

后面代码中会看到,对于你的驱动提交的DMA请求,此DMA驱动内部会自动帮你转换成对应的一个个LLI,此数值就是限制一次DMA请求中,最大支持多少个LLI

4

一些全局的寄存器的偏移地址,这些值都是根据datasheet中定义出来的

5

DMA控制器,有很多个通道channel,每个channel都对应有自己的一些寄存器,下面就是这些寄存器的地址偏移和位域值的含义

6

下面这几个宏定义,好像没用到

7

下面这个宏定义,好像也没用到,具体的流控制flow control的设置以及宏定义,在对应头文件中:

#define PL08X_CCFG_FCTL_MEM_TO_MEM		(0)
#define PL08X_CCFG_FCTL_MEM_TO_PERI		(1)